Z8F4822AR020SG Datasheet, PDF (244/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
224
Figure 57 and Table 122 provide timing information for UART pins for the case where the
Clear To Send input signal (CTS) is not used for flow control. In this example, it is
assumed that the Driver Enable polarity has been configured to be Active Low and is rep-
resented here by DE. DE asserts after the UART Transmit Data Register has been written.
DE remains asserted for multiple characters as long as the Transmit Data Register is writ-
ten with the next character before the current character has completed.
DE
(Output)
TxD
(Output)
T₁
Start Bit 0 Bit 1
T₂
Bit 7 Parity ^Stop
Figure 57. UART Timing without CTS
End of
Stop Bit(s)
Table 122. UART Timing without CTS
Parameter Abbreviation
T₁
DE Assertion to TxD Falling Edge (Start) Delay
T₂
End of stop bit(s) to DE Deassertion Delay
Delay (ns)
Minimum
1 bit period
1 * X_IN period
Maximum
1 bit period +
1 * X_IN period
2 * X_IN period
PS019924-0113
PRELIMINARY
AC Characteristics