Z8F4822AR020SG Datasheet, PDF (121/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
101
Bit
[2]
TDRE
[1]
TXE
[0]
CTS
Description (Continued)
Transmitter Data Register Empty
This bit indicates that the UART Transmit Data Register is empty and ready for additional data.
Writing to the UART Transmit Data Register resets this bit.
0 = Do not write to the UART Transmit Data Register.
1 = The UART Transmit Data Register is ready to receive an additional byte to be transmitted.
Transmitter Empty
This bit indicates that the Transmit Shift Register is empty and character transmission is fin-
ished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTS Signal
When this bit is read, it returns the level of the CTS signal.
UART Status 1 Register
The UART Status 1 Register, shown in Table 56, contains multiprocessor control and
UART status bits.
Table 56. UART Status 1 Register (UxSTAT1)
Bit
7
Field
RESET
R/W
Address
6
5
4
3
2
Reserved
0
R
R/W
F44H and F4CH
1
0
NEWFRM MPRX
R
Bit
[7:2]
[1]
NEWFRM
[0]
MPRX
Description
Reserved
These bits are reserved and must be programmed to 000000.
New Frame
Status bit denoting the start of a new frame. Reading the UART Receive Data Register
resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
Multiprocessor Receive
Returns the value of the last multiprocessor bit received. Reading from the UART Receive
Data Register resets this bit to 0.
PS019924-0113
PRELIMINARY
UART Control Register Definitions