Z8F4822AR020SG Datasheet, PDF (259/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
239
Table 136. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
LDX dst, src
Symbolic Operation
dst ← src
Address
Mode
dst src
r ER
Opcode(s)
Flags
Fetch Instr.
(Hex) C Z S V D H Cycles Cycles
84
–––––– 3
2
Ir ER
85
3
3
R IRR
86
3
4
IR IRR
87
3
5
r X(rr)
88
3
4
X(rr) r
89
3
4
ER r
94
3
2
ER Ir
95
3
3
IRR R
96
3
4
IRR IR
97
3
5
ER ER
E8
4
2
LEA dst, X(src) dst ← src + X
ER IM
E9
4
2
r X(r)
98
–––––– 3
3
rr X(rr)
99
3
5
MULT dst
dst[15:0] ← 
RR
F4
–––––– 2
8
dst[15:8] * dst[7:0]
NOP
OR dst, src
No operation
dst ← dst OR src
0F
–––––– 1
2
r
r
42
–* *0–– 2
3
r Ir
43
2
4
RR
44
3
3
R IR
45
3
4
R IM
46
3
3
IR IM
47
3
4
ORX dst, src dst ← dst OR src
ER ER
48
–* *0–– 4
3
POP dst
dst ← @SP
SP ← SP + 1
ER IM
49
4
3
R
50
–––––– 2
2
IR
51
2
3
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS019924-0113
PRELIMINARY
eZ8 CPU Instruction Summary