Z8F4822AR020SG Datasheet, PDF (49/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
29
System Reset
During a system reset, the Z8 Encore! XP F64xx Series devices are held in Reset for 66
cycles of the Watchdog Timer oscillator followed by 16 cycles of the system clock. At the
beginning of Reset, all GPIO pins are configured as inputs.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run. The system clock begins operat-
ing following the Watchdog Timer oscillator cycle count. The eZ8 CPU and on-chip
peripherals remain idle through the 16 cycles of the system clock.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at program memory addresses 0002H and 0003H and loads
that value into the Program Counter. Program execution begins at the Reset vector
address.
Reset Sources
Table 9 lists the reset sources as a function of the operating mode. The text following pro-
vides more detailed information about the individual Reset sources. A Power-On Reset/
Voltage Brown-Out event always takes priority over all other possible reset sources to
ensure a full system reset occurs.
Table 9. Reset Sources and Resulting Reset Type
Operating Mode
NORMAL or HALT
modes
STOP Mode
Reset Source
Reset Type
Power-On Reset/Voltage Brown- system reset
Out
Watchdog Timer time-out
when configured for Reset
system reset
RESET pin assertion
system reset
On-Chip Debugger initiated Reset system reset except the On-Chip Debugger is
(OCDCTL[0] set to 1)
unaffected by the reset
Power-On Reset/Voltage Brown- system reset
Out
RESET pin assertion
system reset
DBG pin driven Low
system reset
PS019924-0113
PRELIMINARY
Reset Sources