Z8F4822AR020SG Datasheet, PDF (185/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
165
DMA Control of the ADC
The Direct Memory Access (DMA) Controller can control operation of the ADC includ-
ing analog input selection and conversion enable. For more information about the DMA
and configuring for ADC operations, see the Direct Memory Access Controller chapter on
page 150.
ADC Control Register Definitions
This section defines the features of the following ADC Control registers.
ADC Control Register: see page 165
ADC Data High Byte Register: see page 167
ADC Data Low Bits Register: see page 168
ADC Control Register
The ADC Control Register selects the analog input channel and initiates the analog-to-dig-
ital conversion.
Table 87. ADC Control Register (ADCCTL)
Bit
7
6
5
4
3
2
1
0
Field
CEN Reserved VREF CONT
ANAIN[3:0]
RESET
0
1
0
R/W
R/W
Address
F70H
Bit
[7]
CEN
[6]
[5]
VREF
Description
Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion has been completed.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already in
progress, the conversion restarts. This bit remains 1 until the conversion is complete.
Reserved
This bit is reserved and must be programmed to 0.
Voltage Reference
0 = Internal voltage reference generator enabled. The V_REF pin should be left unconnected
(or capacitively coupled to analog ground) if the internal voltage reference is selected as
the ADC reference voltage.
1 = Internal voltage reference generator disabled. An external voltage reference must be
provided through the V_REF pin.
PS019924-0113
PRELIMINARY
ADC Control Register Definitions