Z8F4822AR020SG Datasheet, PDF (117/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
97
byte indicating an overrun error, the Receive Data Register must be read again to clear the
error bits is the UART Status 0 Register. Updates to the Receive Data Register occur only
when the next data word is received.
UART Data and Error Handling Procedure
Figure 18 displays the recommended procedure for use in UART receiver interrupt service
routines.
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 18. UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the Baud Rate Generator interrupt enable is set, the UART Receiver interrupt asserts
when the UART Baud Rate Generator reloads. This action allows the Baud Rate Genera-
tor to function as an additional counter if the UART functionality is not employed.
PS019924-0113
PRELIMINARY
Operation