Z8F4822AR020SG Datasheet, PDF (61/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
41
Port A–H Control Registers
The Port A–H Control registers, shown in Table 15, set the GPIO port operation. The
value in the corresponding Port A–H Address Register determines the control subregisters
accessible using the Port A–H Control Register.
Table 15. Port A–H Control Registers (PxCTL)
Bit
7
6
5
4
3
2
1
0
Field
PCTL
RESET
00H
R/W
R/W
Address
FD1H, FD5H, FD9H, FDDH, FE1H, FE5H, FE9H, FEDH
Bit
[7:0]
PCTL
Description
Port Control
The Port Control Register provides access to all subregisters that configure the GPIO Port
operation.
Port A–H Data Direction Subregisters
The Port A–H Data Direction Subregister, shown in Table 16, is accessed through the Port
A–H Control Register by writing 01H to the Port A–H Address Register.
Table 16. Port A–H Data Direction Subregisters
Bit
7
6
5
4
3
2
1
0
Field
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
RESET
1
R/W
R/W
Address
See note.
Note: If a 01H exists in the Port A–H Address Register, it is accessible through the Port A–H Control Register.
Bit
Description
[7:0]
DDx
Data Direction
These bits control the direction of the associated port pin. Port Alternate Function operation
overrides the Data Direction Register setting.
0 = Output. Data in the Port A–H Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–H Input Data Register.
The output driver is tri-stated.
Note: x indicates register bits in the range [7:0].
PS019924-0113
PRELIMINARY
GPIO Control Register Definitions