Z8F4822AR020SG Datasheet, PDF (174/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
154
Bit
[3]
WSEL
[2:0]
RSS
Description (Continued)
Word Select
0 = DMAx transfers a single byte per request.
1 = DMAx transfers a two-byte word per request. The address for the on-chip peripheral con-
trol register must be an even address.
Request Trigger Source Select
The Request Trigger Source Select field determines the peripheral that can initiate a DMA
transfer. The corresponding interrupts do not need to be enabled within the Interrupt Controller
to initiate a DMA transfer. However, if the Request Trigger Source can enable or disable the
interrupt request sent to the Interrupt Controller, the interrupt request must be enabled within
the Request Trigger Source block.
000 = Timer 0.
001 = Timer 1.
010 = Timer 2.
011 = Timer 3.
100 = DMA0 Control Register: UART0 Received Data Register contains valid data. DMA1
Control Register: UART0 Transmit Data Register empty.
101 = DMA0 Control Register: UART1 Received Data Register contains valid data. DMA1
Control Register: UART1 Transmit Data Register empty.
110 = DMA0 Control Register: I²C Receiver Interrupt. DMA1 Control Register: I²C Transmitter
Interrupt Register empty.
111 = Reserved.
DMAx I/O Address Register
The DMAx I/O Address Register, shown in Table 79, contains the low byte of the on-chip
peripheral address for data transfer. The full 12-bit Register File address is provided by
{FH, DMAx_IO[7:0]}. When the DMA is configured for two-byte word transfers, the
DMAx I/O Address Register must contain an even-numbered address.
Table 79. DMAx I/O Address Register (DMAxIO)
Bit
7
6
5
4
3
2
1
0
Field
DMA_IO
RESET
X
R/W
R/W
Address
FB1H, FB9H
Bit
Description
[7:0]
DMA On-Chip Peripheral Control Register Address
DMA_IO This byte sets the low byte of the on-chip peripheral control register address on Register File
Page FH (addresses F00H to FFFH).
PS019924-0113
PRELIMINARY
DMA Control Register Definitions