Z8F4822AR020SG Datasheet, PDF (137/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
117
Table 63. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
PHASE
0
0
1
1
CLKPOL
0
1
0
1
SCK Transmit
Edge
Falling
Rising
Rising
Falling
SCK Receive
Edge
Rising
Falling
Falling
Rising
SCK Idle
State
Low
High
Low
High
Transfer Format PHASE Equals Zero
Figure 25 displays the timing diagram for an SPI transfer in which PHASE is cleared to 0.
The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to
one. The diagram may be interpreted as either a Master or Slave timing diagram because
the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly
connected between the Master and the Slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MISO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Input Sample Time
SS
Figure 25. SPI Timing When PHASE is 0
PS019924-0113
PRELIMINARY
Operation