Z8F4822AR020SG Datasheet, PDF (165/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
145
Bit
[1]
FLUSH
[0]
FILTEN
Description (Continued)
Flush Data
Setting this bit to 1 clears the I²C Data Register and sets the TDRE bit to 1. This bit allows
flushing of the I²C Data Register when a Not Acknowledge interrupt is received after the data
has been sent to the I²C Data Register. Reading this bit always returns 0.
I²C Signal Filter Enable
This bit enables low-pass digital filters on the SDA and SCL input signals. These filters reject
any input pulse with periods less than a full system clock cycle. The filters introduce a 3-sys-
tem clock cycle latency on the inputs.
1 = low-pass filters are enabled.
0 = low-pass filters are disabled.
I²C Baud Rate High and Low Byte Registers
The I²C Baud Rate High and Low Byte registers, shown in Tables 74 and 75, combine to
form a 16-bit reload value, BRG[15:0], for the I²C Baud Rate Generator.
When the I²C is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the I²C by clearing the IEN bit in the I²C Control Register to 0.
2. Load the appropriate 16-bit count value into the I²C Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the I²C Control Register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s)  BRG15:0
PS019924-0113
PRELIMINARY
I2C Control Register Definitions