Z8F4822AR020SG Datasheet, PDF (241/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
221
SPI Slave Mode Timing
Figure 54 and Table 119 provide timing information for the SPI slave mode pins. Timing
is shown with SCK rising edge used to source MISO output data, SCK falling edge used to
sample MOSI input data.
SCK
T1
MISO
(Output)
MOSI
(Input)
T4
SS
(Input)
Output Data
T2 T3
Input Data
Figure 54. SPI Slave Mode Timing
Table 119. SPI Slave Mode Timing
Parameter
SPI Slave
T₁
Abbreviation
SCK (transmit edge) to MISO output Valid Delay
T₂
MOSI input to SCK (receive edge) Setup Time
T₃
MOSI input to SCK (receive edge) Hold Time
T₄
SS input assertion to SCK setup
Delay (ns)
Minimum
Maximum
2 * X_IN period 3 * X_IN period +
20 nsec
0
3 * X_IN period
1 * X_IN period
PS019924-0113
PRELIMINARY
AC Characteristics