Z8F4822AR020SG Datasheet, PDF (59/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
39
Table 12. Port Alternate Function Mapping (Continued)
Port
Port F
Port G
Port H
Pin Mnemonic
PF[7:0] N/A
PG[7:0] N/A
PH0 ANA8
PH1 ANA9
PH2 ANA10
PH3 ANA11
Alternate Function Description
No alternate functions
No alternate functions
ADC analog input 8
ADC analog input 9
ADC analog input 10
ADC analog input 11
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be con-
figured to generate an interrupt request on either the rising edge or falling edge of the pin
input signal. Other port pin interrupts generate an interrupt when any edge occurs (both
rising and falling). For more information about interrupts using the GPIO pins, see the
Interrupt Controller chapter on page 47.
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 13 lists these Port registers. Use the Port A–H Address and Control registers
together to provide access to subregisters for Port configuration and control.
Table 13. GPIO Port Registers and Subregisters
Port Register
Mnemonic
PxADDR
PxCTL
PxIN
PxOUT
Port Subregister
Mnemonic
PxDD
PxAF
PxOC
PxDD
PxSMRE
Port Register Name
Port A–H Address Register (selects subregisters)
Port A–H Control Register (provides access to subregisters)
Port A–H Input Data Register
Port A–H Output Data Register
Port Register Name
Data Direction
Alternate Function
Output Control (Open-Drain)
High Drive Enable
Stop Mode Recovery Source Enable
PS019924-0113
PRELIMINARY
GPIO Interrupts