Z8F4822AR020SG Datasheet, PDF (208/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
188
interrupts are typically disabled during critical sections of code where interrupts should
not occur (such as adjusting the stack pointer or modifying shared data).
Software can poll the IDLE bit of the OCDSTAT Register to determine if the OCD is loop-
ing on a BRK instruction. When software stops the CPU on the BRK instruction that it is
looping on, it should not set the DBGMODE bit of the OCDCTL Register. The CPU may
have vectored to and be in the middle of an interrupt service routine when this bit gets set.
Instead, software must clear the BRKLP bit. This action allows the CPU to finish the inter-
rupt service routine it may be in and return the BRK instruction. When the CPU returns to
the BRK instruction it was previously looping on, it automatically sets the DBGMODE bit
and enters DEBUG Mode.
Software detects that the majority of the OCD commands are still disabled when the eZ8
CPU is looping on a BRK instruction. The eZ8 CPU must be stopped and the part must be
in DEBUG Mode before these commands can be issued.
Breakpoints in Flash Memory
The BRK instruction is op code 00H, which corresponds to the fully programmed state of
a byte in Flash memory. To implement a breakpoint, write 00H to the appropriate address,
overwriting the current instruction. To remove a breakpoint, the corresponding page of
Flash memory must be erased and reprogrammed with the original data.
On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are avail-
able. In DEBUG Mode, all OCD commands become available unless the user code and
control registers are protected by programming the Read Protect option bit (RP). The Read
Protect option bit prevents the code in memory from being read out of the Z8 Encore! XP
F64xx Series products. When this option is enabled, several of the OCD commands are
disabled.
Table 102 contains a summary of the On-Chip Debugger commands. Table 102 lists those
commands that operate when the device is not in DEBUG Mode (normal operation) and
those commands that are disabled by programming the Read Protect option bit.
Each OCD command is further described in the list that follows the table.
PS019924-0113
PRELIMINARY
On-Chip Debugger Commands