Z8F4822AR020SG Datasheet, PDF (96/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
76
Timer 0–3 Control 0 Registers
The Timer 0–3 Control 0 (TxCTL0) registers, shown in Tables 45 and 46, allow cascading
of the timers.
Table 45. Timer 0–3 Control 0 Register (TxCTL0)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
CSC
Reserved
RESET
0
R/W
R/W
Address
F06H, F0EH, F16H, F1EH
Bit
[7:5]
[4]
CSC
[3:0]
Description
Reserved
These bits are reserved and must be programmed to 000.
Cascade Timers
0 = Timer input signal comes from the pin.
1 = For Timer 0, the input signal is connected to Timer 3 output.
For Timer 1, the input signal is connected to the Timer 0 output.
For Timer 2, the input signal is connected to the Timer 1 output.
For Timer 3, the input signal is connected to the Timer 2 output.
Reserved
These bits are reserved and must be programmed to 0000.
PS019924-0113
PRELIMINARY
Timer Control Register Definitions