Z8F4822AR020SG Datasheet, PDF (120/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
100
UART Status 0 Register
The UART Status 0 Register, shown in Table 55, identifies the current UART operating
configuration and status.
Table 55. UART Status 0 Register (UxSTAT0)
Bit
7
6
Field
RDA
PE
RESET
R/W
Address
5
4
3
2
1
0
OE
FE
BRKD TDRE
TXE
CTS
0
1
X
R
F41H and F49H
Bit
[7]
RDA
[6]
PE
[5]
OE
[4]
FE
[3]
BRKD
Description
Receive Data Available
This bit indicates that the UART Receive Data Register has received data. Reading the UART
Receive Data Register clears this bit.
0 = The UART Receive Data Register is empty.
1 = There is a byte in the UART Receive Data Register.
Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data Register
clears this bit.
0 = No parity error occurred.
1 = A parity error occurred.
Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data Register has not been read. If the RDA bit is reset to 0,
then reading the UART Receive Data Register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
Framing Error
This bit indicates that a framing error (no stop bit following data reception) was detected. Read-
ing the UART Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and stop bit(s)
are all zeros then this bit is set to 1. Reading the UART Receive Data Register clears this bit.
0 = No break occurred.
1 = A break occurred.
PS019924-0113
PRELIMINARY
UART Control Register Definitions