Z8F4822AR020SG Datasheet, PDF (146/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
126
SPI Diagnostic State Register
The SPI Diagnostic State Register, shown in Table 68, provides observability of internal
state. This register is a read-only register that is used for SPI diagnostics.
Table 68. SPI Diagnostic State Register (SPIDST)
Bit
7
6
5
4
3
2
1
0
Field
SCKEN TCKEN
SPISTATE
RESET
0
R/W
R
Address
F64H
Bit
[7]
SCKEN
[6]
TCKEN
[5:0]
SPISTATE
Description
Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted.
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next sys-
tem clock).
Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).
SPI State Machine
Defines the current state of the internal SPI State Machine.
SPI Baud Rate High and Low Byte Registers
The SPI Baud Rate High and Low Byte registers, shown in Tables 69 and 70, combine to
form a 16-bit reload value, BRG[15:0], for the SPI Baud Rate Generator.
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
SPI BRG Interrupt Interval (s) = System Clock Period (s)  BRG[15:0]
PS019924-0113
PRELIMINARY
SPI Control Register Definitions