Z8F4822AR020SG Datasheet, PDF (101/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
81
WDT Reload
Value
(Hex)
000004
FFFFFF
Table 47. Watchdog Timer Approximate Time-Out Delays
WDT Reload
Value
(Decimal)
4
16,777,215
Approximate Time-Out Delay
(with 10 kHz typical WDT Oscillator Frequency)
Typical
Description
400 µs
Minimum time-out delay
1677.5 s
Maximum time-out delay
Watchdog Timer Refresh
When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer
Reload registers. The Watchdog Timer then counts down to 000000H unless a WDT
instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the
downcounter to be reloaded with the WDT reload value stored in the Watchdog Timer
Reload registers. Counting resumes following the reload operation.
When the Z8 Encore! XP F64xx Series devices are operating in DEBUG Mode (through
the On-Chip Debugger), the Watchdog Timer is continuously refreshed to prevent spuri-
ous Watchdog Timer time-outs.
Watchdog Timer Time-Out Response
The Watchdog Timer times out when the counter reaches 000000H. A time-out of the
Watchdog Timer generates either an interrupt or a Reset. The WDT_RES option bit deter-
mines the time-out response of the Watchdog Timer. For information about programming
of the WDT_RES option bit, see the Option Bits chapter on page 180.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watchdog
Timer Control Register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watchdog Timer interrupt vector and executing code from the vec-
tor address. After time-out and interrupt generation, the Watchdog Timer counter rolls
over to its maximum value of FFFFFH and continues counting. The Watchdog Timer
counter is not automatically returned to its reload value.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and the Z8 Encore! XP
F64xx Series devices are in STOP Mode, the Watchdog Timer automatically initiates a
Stop Mode Recovery and generates an interrupt request. Both the WDT status bit and the
stop bit in the Watchdog Timer Control Register are set to 1 following WDT time-out in
PS019924-0113
PRELIMINARY
Operation