Z8F4822AR020SG Datasheet, PDF (260/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
240
Table 136. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
POPX dst
PUSH src
Symbolic Operation
dst ← @SP
SP ← SP + 1
SP ← SP – 1
@SP ← src
Address
Mode
dst src
ER
R
IR
IM
PUSHX src SP ← SP – 1
ER
@SP ← src
RCF
C←0
RET
PC ← @SP
SP ← SP + 2
RL dst
R
RLC dst
RR dst
C
D7 D6 D5 D4 D3 D2 D1 D0
IR
dst
R
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
R
D7 D6 D5 D4 D3 D2 D1 D0
dst
C _IR
RRC dst
R
D7 D6 D5 D4 D3 D2 D1 D0
C
dst
IR
SBC dst, src dst ← dst – src – C
r
r
r Ir
RR
R IR
R IM
SBCX dst, src dst ← dst – src – C
IR IM
ER ER
SCF
C←1
ER IM
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
Opcode(s)
Flags
Fetch Instr.
(Hex) C Z S V D H Cycles Cycles
D8
–––––– 3
2
70
–––––– 2
2
71
2
3
1F 70
3
2
C8
–––––– 3
2
CF
0––––– 1
2
AF
–––––– 1
4
90
* * * *–– 2
2
91
2
3
10
* * * *–– 2
2
11
2
3
E0
* * * *–– 2
2
E1
2
3
C0
* * * *–– 2
2
C1
2
3
32
****1* 2
3
33
2
4
34
3
3
35
3
4
36
3
3
37
3
4
38
****1* 4
3
39
4
3
DF
1––––– 1
2
PS019924-0113
PRELIMINARY
eZ8 CPU Instruction Summary