Z8F4822AR020SG Datasheet, PDF (67/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
47
Interrupt Controller
The interrupt controller on the Z8 Encore! XP F64xx Series products prioritizes the inter-
rupt requests from the on-chip peripherals and the GPIO port pins. The features of the
interrupt controller include:
• 24 unique interrupt vectors:
– 12 GPIO port pin interrupt sources
– 12 on-chip peripheral interrupt sources
• Flexible GPIO interrupts
– Eight selectable rising and falling edge GPIO interrupts
– Four dual-edge interrupts
• Three levels of individually programmable interrupt priority
• Watchdog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. For more information about interrupt ser-
vicing by the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is
available for download on www.zilog.com.
Interrupt Vector Listing
Table 23 lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most significant byte (MSB) at the even program memory address and the
least significant byte (LSB) at the following odd program memory address.
PS019924-0113
PRELIMINARY
Interrupt Controller