Z8F4822AR020SG Datasheet, PDF (255/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
235
Table 136. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
ADD dst, src
Symbolic Operation
dst ← dst + src
Address
Mode
dst src
r
r
r Ir
RR
R IR
R IM
ADDX dst, src dst ← dst + src
IR IM
ER ER
AND dst, src dst ← dst AND src
ER IM
r
r
r Ir
RR
R IR
R IM
ANDX dst, src dst ← dst AND src
IR IM
ER ER
ER IM
ATM
Block all interrupt and
DMA requests during
execution of the next 3
instructions
BCLR bit, dst dst[bit] ← 0
r
BIT p, bit, dst dst[bit] ← p
r
BRK
Debugger Break
BSET bit, dst dst[bit] ← 1
r
BSWAP dst dst[7:0] ← dst[0:7]
R
BTJ p, bit, src, if src[bit] = p
r
dst
PC ← PC + X
Ir
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
Opcode(s)
Flags
Fetch Instr.
(Hex) C Z S V D H Cycles Cycles
02
****0* 2
3
03
2
4
04
3
3
05
3
4
06
3
3
07
3
4
08
****0* 4
3
09
4
3
52
–* *0–– 2
3
53
2
4
54
3
3
55
3
4
56
3
3
57
3
4
58
–* *0–– 4
3
59
4
3
2F
–––––– 1
2
E2
–––––– 2
2
E2
–––––– 2
2
00
–––––– 1
1
E2
–––––– 2
2
D5
X* *0–– 2
2
F6
–––––– 3
3
F7
3
4
PS019924-0113
PRELIMINARY
eZ8 CPU Instruction Summary