Z8F4822AR020SG Datasheet, PDF (163/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
143
Bit
[5]
ACK
[4]
10B
[3]
RD
[2]
TAS
[1]
DSS
[0]
NCKI
Description (Continued)
Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received. When
set, this bit indicates that an Acknowledge occurred for the last byte transmitted or received.
This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the last byte trans-
mitted or received. It is not reset at the beginning of each transaction and is not reset when this
register is read.
Caution: When making decisions based on this bit within a transaction, software cannot deter-
mine when the bit is updated by hardware. In the case of write transactions, the I²C pauses at
the beginning of the Acknowledge cycle if the next transmit data or address byte has not been
written (TDRE = 1) and stop and start = 0. In this case the ACK bit is not updated until the
transmit interrupt is serviced and the Acknowledge cycle for the previous byte completes. For
examples of how the ACK bit can be used, see the Address Only Transaction with a 7-bit
Address section on page 133 and the Address Only Transaction with a 10-bit Address section
on page 135.
10-Bit Address
This bit indicates whether a 10- or 7-bit address is being transmitted. After the start bit is set, if
the five most significant bits of the address are 11110B, this bit is set. When set, it is reset
once the first byte of the address has been sent.
Read
This bit indicates the direction of transfer of the data. It is active High during a read. The status
of this bit is determined by the least significant bit of the I²C Shift Register after the start bit is
set.
Transmit Address State
This bit is active High while the address is being shifted out of the I²C Shift Register.
Data Shift State
This bit is active High while data is being shifted to or from the I²C Shift Register.
NACK Interrupt
This bit is set High when a Not Acknowledge condition is received or sent and neither the start
nor the stop bit is active. When set, this bit generates an interrupt that can only be cleared by
setting the start or stop bit, allowing you to specify whether to perform a stop or a repeated
start.
PS019924-0113
PRELIMINARY
I2C Control Register Definitions