Z8F4822AR020SG Datasheet, PDF (114/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
94
In MULTIPROCESSOR (9-Bit) Mode, the parity bit location (9th bit) becomes the MUL-
TIPROCESSOR control bit. The UART Control 1 and Status 1 registers provide MULTI-
PROCESSOR (9-Bit) Mode control and status information. If an automatic address
matching scheme is enabled, the UART Address Compare Register holds the network
address of the device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When MULTIPROCESSOR Mode is enabled, the UART only processes frames addressed
to it. The determination of whether a frame of data is addressed to the UART can be made
in hardware, software or some combination of the two, depending on the multiprocessor
configuration bits. In general, the address compare feature reduces the load on the CPU,
since it does not need to access the UART when it receives data directed to other devices
on the multinode network. The following three MULTIPROCESSOR modes are available
in hardware:
• Interrupt on all address bytes
• Interrupt on matched address bytes and correctly framed data bytes
• Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all
MULTIPROCESSOR modes, bit MPEN of the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine must manually check the address byte that caused triggered the interrupt. If
it matches the UART address, the software clears MPMD[0]. At this point, each new
incoming byte interrupts the CPU. The software is then responsible for determining the
end of the frame. It checks for end-of-frame by reading the MPRX bit of the UART Status
1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of
this new frame is different from the UART’s address, then set MPMD[0] to 1 causing the
UART interrupts to go inactive until the next address byte. If the new frame’s address
matches the UART’s, the data in the new frame is processed as well.
The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UART’s
address into the UART Address Compare Register. This mode introduces more hardware
control, interrupting only on frames that match the UART’s address. When an incoming
address byte does not match the UART’s address, it is ignored. All successive data bytes in
this frame are also ignored. When a matching address byte occurs, an interrupt is issued
and further interrupts now occur on each successive data byte. The first data byte in the
frame contains the NEWFRM = 1 in the UART Status 1 Register. When the next address
byte occurs, the hardware compares it to the UART’s address. If there is a match, the inter-
rupts continue sand the NEWFRM bit is set for the first byte of the new frame. If there is
no match, then the UART ignores all incoming bytes until the next address match.
PS019924-0113
PRELIMINARY
Operation