Z8F4822AR020SG Datasheet, PDF (164/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
144
I²C Control Register
The I²C Control Register, shown in Table 73, enables I²C operation.
Table 73. I²C Control Register (I2CCTL)
Bit
7
Field
IEN
RESET
R/W
R/W
Address
6
START
5
STOP
R/W1
R/W1
4
3
BIRQ
TXI
0
R/W
R/W
F52H
2
NAK
1
FLUSH
0
FILTEN
R/W1
W1
R/W
Bit
[7]
IEN
[6]
START
[5]
STOP
[4]
BIRQ
[3]
TXI
[2]
NAK
Description
I²C Enable
1 = The I²C transmitter and receiver are enabled.
0 = The I²C transmitter and receiver are disabled.
Send Start Condition
This bit sends the Start condition. Once asserted, it is cleared by the I²C Controller after it
sends the START condition or if the IEN bit is deasserted. If this bit is 1, it cannot be cleared to
0 by writing to the register. After this bit is set, the Start condition is sent if there is data in the
I²C Data Register or I²C Shift Register. If there is no data in one of these registers, the I²C
Controller waits until the Data Register is written. If this bit is set while the I²C Controller is
shifting out data, it generates a start condition after the byte shifts and the acknowledge phase
completes. If the stop bit is also set, it also waits until the stop condition is sent before the
sending the start condition.
Send Stop Condition
This bit causes the I²C Controller to issue a Stop condition after the byte in the I²C Shift Regis-
ter has completed transmission or after a byte has been received in a receive operation. AFter
it is set, this bit is reset by the I²C Controller after a Stop condition has been sent or by deas-
serting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the register.
Baud Rate Generator Interrupt Request
This bit allows the I²C Controller to be used as an additional timer when the I²C Controller is
disabled. This bit is ignored when the I²C Controller is enabled.
1 = An interrupt occurs every time the baud rate generator counts down to one.
0 = No baud rate generator interrupt occurs.
Enable TDRE Interrupts
This bit enables the transmit interrupt when the I²C Data Register is empty (TDRE = 1).
1 = Transmit interrupt (and DMA transmit request) is enabled.
0 = Transmit interrupt (and DMA transmit request) is disabled.
Send NAK
This bit sends a Not Acknowledge condition after the next byte of data has been read from the
I²C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN bit is
deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register.
PS019924-0113
PRELIMINARY
I2C Control Register Definitions