Z8F4822AR020SG Datasheet, PDF (150/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
130
SDA and SCL Signals
I²C sends all addresses, data and acknowledge signals over the SDA line, most significant
bit first. SCL is the common clock for the I²C Controller. When the SDA and SCL pin
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master (I²C) is responsible for driving the SCL clock signal, although the clock signal
can become skewed by a slow slave device. During the low period of the clock, the slave
pulls the SCL signal Low to suspend the transaction. The master releases the clock at the
end of the low period and notices that the clock remains low instead of returning to a High
level. When the slave releases the clock, the I²C Controller continues the transaction. All
data is transferred in bytes and there is no limit to the amount of data transferred in one
operation. When transmitting data or acknowledging read data from the slave, the SDA
signal changes in the middle of the low period of SCL and is sampled in the middle of the
High period of SCL.
I²C Interrupts
The I²C Controller contains four sources of interrupts—Transmit, Receive, Not Acknowl-
edge and baud rate generator. These four interrupt sources are combined into a single
interrupt request signal to the Interrupt Controller. The transmit interrupt is enabled by the
IEN and TXI bits of the Control Register. The Receive and Not Acknowledge interrupts
are enabled by the IEN bit of the Control Register. The baud rate generator interrupt is
enabled by the BIRQ and IEN bits of the Control Register.
Not Acknowledge interrupts occur when a Not Acknowledge condition is received from
the slave or sent by the I²C Controller and neither the start or stop bit is set. The Not
Acknowledge event sets the NCKI bit of the I²C Status Register and can only be cleared
by setting the start or stop bit in the I²C Control Register. When this interrupt occurs, the
I²C Controller waits until either the stop or start bit is set before performing any action. In
an interrupt service routine, the NCKI bit should always be checked prior to servicing
transmit or receive interrupt conditions because it indicates the transaction is being termi-
nated.
Receive interrupts occur when a byte of data has been received by the I²C Controller
(master reading data from slave). This procedure sets the RDRF bit of the I²C Status Reg-
ister. The RDRF bit is cleared by reading the I²C Data Register. The RDRF bit is set dur-
ing the acknowledge phase. The I²C Controller pauses after the acknowledge phase until
the receive interrupt is cleared before performing any other action.
Transmit interrupts occur when the TDRE bit of the I²C Status Register sets and the TXI
bit in the I²C Control Register is set. transmit interrupts occur under the following condi-
tions when the transmit data register is empty:
• The I²C Controller is enabled
PS019924-0113
PRELIMINARY
Operation