Z8F4822AR020SG Datasheet, PDF (240/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
220
SPI Master Mode Timing
Figure 53 and Table 118 provide timing information for SPI Master Mode pins. Timing is
shown with SCK rising edge used to source MOSI output data, SCK falling edge used to
sample MISO input data. Timing on the SS output pin(s) is controlled by software.
SCK
MOSI
(Output)
MISO
(Input)
T1
Output Data
T2 T3
Input Data
Figure 53. SPI Master Mode Timing
Table 118. SPI Master Mode Timing
Parameter Abbreviation
SPI Master
T₁
SCK Rise to MOSI output Valid Delay
T₂
MISO input to SCK (receive edge) Setup Time
T₃
MISO input to SCK (receive edge) Hold Time
Delay (ns)
Min
Max
–5
+5
20
0
PS019924-0113
PRELIMINARY
AC Characteristics