Z8F4822AR020SG Datasheet, PDF (173/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
153
DMAx Control Register
The DMAx Control Register, shown in Table 78, enables and selects the mode of opera-
tion for DMAx.
Table 78. DMAx Control Register (DMAxCTL)
Bit
7
6
5
4
3
2
1
0
Field
DEN
DLE
DDIR IRQEN WSEL
RSS
RESET
0
R/W
R/W
Address
FB0H, FB8H
Bit
[7]
DEN
[6]
DLE
[5]
DDIR
[4]
IRQEN
Description
DMAx Enable
0 = DMAx is disabled and data transfer requests are disregarded.
1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger
source.
DMAx Loop Enable
0 = DMAx reloads the original Start Address and is then disabled after the End Address data is
transferred.
1 = DMAx, after the End Address data is transferred, reloads the original Start Address and
continues operating.
DMAx Data Transfer Direction
0 = Register File → on-chip peripheral control register.
1 = On-chip peripheral control → Register File.
DMAx Interrupt Enable
0 = DMAx does not generate any interrupts.
1 = DMAx generates an interrupt when the End Address data is transferred.
PS019924-0113
PRELIMINARY
DMA Control Register Definitions