Z8F4822AR020SG Datasheet, PDF (75/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
55
IRQ0 Enable High and Low Bit Registers
Table 27 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters, shown in Tables 28 and 29, form a priority-encoded enabling for interrupts in the
Interrupt Request 0 Register. Priority is generated by setting bits in each register.
Table 27. IRQ0 Enable and Priority Encoding
IRQ0ENH[x]
IRQ0ENL[x]
Priority
0
0
Disabled
0
1
Level 1
1
0
Level 2
1
1
Level 3
Note: x indicates register bits in the range [7:0].
Description
Disabled
Low
Nominal
High
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH)
Bit
Field
RESET
R/W
Address
7
T2ENH
6
T1ENH
5
T0ENH
4
3
U0RENH U0TENH
0
R/W
FC1H
2
I2CENH
1
0
SPIENH ADCENH
Bit
Description
[7]
Timer 2 Interrupt Request Enable High Bit
T2ENH
[6]
Timer 1 Interrupt Request Enable High Bit
T1ENH
[5]
Timer 0 Interrupt Request Enable High Bit
T0ENH
[4]
UART 0 Receive Interrupt Request Enable High Bit
U0RENH
[3]
UART 0 Transmit Interrupt Request Enable High Bit
U0TENH
[2]
I²C Interrupt Request Enable High Bit
I2CENH
[1]
SPI Interrupt Request Enable High Bit
SPIENH
[0]
ADC Interrupt Request Enable High Bit
ADCENH
PS019924-0113
PRELIMINARY
Interrupt Control Register Definitions