Z8F4822AR020SG Datasheet, PDF (132/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
112
since the previous pulse was detected). This gives the endec a sampling window of minus
four baud rate clocks to plus eight baud rate clocks around the expected time of an incom-
ing pulse. If an incoming pulse is detected inside this window this process is repeated. If
the incoming data is a logical 1 (no pulse), the endec returns to the initial state and waits
for the next falling edge. As each falling edge is detected, the endec clock counter is reset,
resynchronizing the endec to the incoming signal. This action allows the endec to tolerate
jitter and baud rate errors in the incoming data stream. Resynchronizing the endec does
not alter the operation of the UART, which ultimately receives the data. The UART is only
synchronized to the incoming data stream when a start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All infrared endec configuration and status information is set by the UART control regis-
ters as defined in the UART Control Register Definitions section on page 98.
Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the
UARTx Control 1 Register to 1 to enable the Infrared Encoder/Decoder before enabling
the GPIO Port alternate function for the corresponding pin.
PS019924-0113
P R E L I M I N A R Y Infrared Encoder/Decoder Control Register