Z8F4822AR020SG Datasheet, PDF (207/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
187
If the OCD receives a serial break (nine or more continuous bits Low) the Autobaud
Detector/Generator resets. The Autobaud Detector/Generator can then be reconfigured by
sending 80H.
OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
• Serial break (a minimum of nine continuous bits Low)
• Framing error (received stop bit is Low)
• Transmit collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a serial break 4096 system clock cycles long back to the host, and resets the
Autobaud Detector/Generator. A framing error or transmit collision may be caused by the
host sending a serial break to the OCD. Because of the open-drain nature of the interface,
returning a serial break back to the host only extends the length of the serial break if the
host releases the serial break early.
The host transmits a serial break on the DBG pin when first connecting to the Z8 Encore!
XP F64xx Series devices or when recovering from an error. A serial break from the host
resets the Autobaud Generator/Detector but does not reset the OCD Control Register. A
serial break leaves the device in DEBUG Mode if that is the current mode. The OCD is
held in Reset until the end of the serial break when the DBG pin returns High. Because of
the open-drain nature of the DBG pin, the host can send a serial break to the OCD even if
the OCD is transmitting a character.
Breakpoints
Execution breakpoints are generated using the BRK instruction (op code 00H). When the
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If breakpoints are
enabled, the OCD idles the eZ8 CPU and enters DEBUG Mode. If breakpoints are not
enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP.
If breakpoints are enabled, the OCD can be configured to automatically enter DEBUG
Mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU is still enabled to service DMA and interrupt requests.
The loop on BRK instruction can be used to service interrupts in the background. For
interrupts to be serviced in the background, there cannot be any breakpoints in the inter-
rupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine.
For interrupts to be serviced in the background, interrupts must also be enabled. Debug-
ging software should not automatically enable interrupts when using this feature, since
PS019924-0113
PRELIMINARY
Operation