Z8F4822AR020SG Datasheet, PDF (81/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
61
Interrupt Control Register
The Interrupt Control (IRQCTL) Register, shown in Table 38, contains the master enable
bit for all interrupts.
Table 38. Interrupt Control Register (IRQCTL)
Bit
7
6
5
4
3
2
1
0
Field
IRQE
Reserved
RESET
0
R/W
R/W
R
Address
FCFH
Bit
[7]
IRQE
[6:0]
Description
Interrupt Request Enable
This bit is set to 1 by execution of an EI or IRET instruction, or by a direct register write of a 1
to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of an inter-
rupt request, or a Reset.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved
These pins are reserved and must be programmed to 000000.
PS019924-0113
PRELIMINARY
Interrupt Control Register Definitions