Z8F4822AR020SG Datasheet, PDF (155/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
135
16. The I²C Controller completes transmission of the data on the SDA signal.
17. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
the stop or start bit is already set, the NCKI interrupt does not occur.
18. The I²C Controller sends the stop (or RESTART) condition to the I²C bus. The stop or
start bit is cleared.
Address Only Transaction with a 10-bit Address
In the situation where software wants to determine if a slave with a 10-bit address is
responding without sending or receiving data, a transaction can be done which only con-
sists of an address phase. Figure 30 displays this address only transaction to determine if a
slave with 10-bit address will acknowledge. As an example, this transaction can be used
after a write has been performed to an EEPROM to determine when the EEPROM com-
pletes its internal write operation and is again responding to I²C transactions. If the slave
does not Acknowledge the transaction can be repeated until the slave is able to Acknowl-
edge.
S
Slave Address
1st 7 bits
W = 0 A/A
Slave Address
2nd Byte
A/A P
Figure 30. 10-Bit Address Only Transaction Format
Observe the following procedure for an address only transaction to a 10-bit addressed
slave:
1. Software asserts the IEN bit in the I²C Control Register.
2. Software asserts the TXI bit of the I²C Control Register to enable transmit interrupts.
3. The I²C interrupt asserts, because the I²C Data Register is empty (TDRE = 1)
4. Software responds to the TDRE interrupt by writing the first slave address byte. The
least significant bit must be 0 for the write operation.
5. Software asserts the start bit of the I²C Control Register.
6. The I²C Controller sends the start condition to the I²C slave.
7. The I²C Controller loads the I²C Shift Register with the contents of the I²C Data Reg-
ister.
8. After one bit of address is shifted out by the SDA signal, the transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I²C
Data Register.
PS019924-0113
PRELIMINARY
Operation