Z8F4822AR020SG Datasheet, PDF (103/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
83
unlock the Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write
access.
1. Write 55H to the Watchdog Timer Control Register (WDTCTL).
2. Write AAH to the Watchdog Timer Control Register (WDTCTL).
3. Write the Watchdog Timer Reload Upper Byte Register (WDTU).
4. Write the Watchdog Timer Reload High Byte Register (WDTH).
5. Write the Watchdog Timer Reload Low Byte Register (WDTL).
All steps of the Watchdog Timer reload unlock sequence must be written in the sequence
described above; there must be no other register writes between each of these operations.
If a register write occurs, the lock state machine resets and no further writes can occur,
unless the sequence is restarted. The value in the Watchdog Timer Reload registers is
loaded into the counter when the Watchdog Timer is first enabled and every time a WDT
instruction is executed.
Watchdog Timer Control Register Definitions
This section defines the features of the following Watchdog Timer Control registers.
Watchdog Timer Control Register: see page 83
Watchdog Timer Reload Upper, High and Low Byte Registers: see page 85
Watchdog Timer Control Register
The Watchdog Timer Control (WDTCTL) Register, shown in Table 48, is a read-only reg-
ister that indicates the source of the most recent Reset event, indicates a Stop Mode
Recovery event, and indicates a Watchdog Timer time-out. Reading this register resets the
upper four bits to 0.
Writing the 55H, AAH unlock sequence to the Watchdog Timer Control (WDTCTL) Regis-
ter address unlocks the three Watchdog Timer Reload Byte registers (WDTU, WDTH, and
WDTL) to allow changes to the time-out period. These write operations to the WDTCTL
Register address produce no effect on the bits in the WDTCTL Register. The locking
mechanism prevents spurious writes to the Reload registers.
PS019924-0113
PRELIMINARY
Watchdog Timer Control Register