Z8F4822AR020SG Datasheet, PDF (74/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
54
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) Register, shown in Table 26, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
Table 26. Interrupt Request 2 Register (IRQ2)
Bit
7
Field
T3I
RESET
R/W
Address
6
U1RXI
5
U1TXI
4
3
DMAI
PC3I
0
R/W
FC6H
2
PC2I
1
PC1I
0
PC0I
Bit
Description
[7]
Timer 3 Interrupt Request
T3I
0 = No interrupt request is pending for Timer 3.
1 = An interrupt request from Timer 3 is awaiting service.
[6]
U1RXI
UART 1 Receive Interrupt Request
0 = No interrupt request is pending for the UART1 receiver.
1 = An interrupt request from UART1 receiver is awaiting service.
[5]
U1TXI
UART 1 Transmit Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
[4]
DMAI
DMA Interrupt Request
0 = No interrupt request is pending for the DMA.
1 = An interrupt request from the DMA is awaiting service.
[3:0]
PCxI
Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Note: x indicates the specific GPIO Port C pin in the range [3:0].
PS019924-0113
PRELIMINARY
Interrupt Control Register Definitions