Z8F4822AR020SG Datasheet, PDF (151/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
131
• The first bit of the byte of an address is shifting out and the RD bit of the I²C Status
Register is deasserted.
• The first bit of a 10-bit address shifts out
• The first bit of write data shifts out
Note: Writing to the I²C Data Register always clears the TRDE bit to 0. When TDRE is asserted,
the I²C Controller pauses at the beginning of the Acknowledge cycle of the byte currently
shifting out. It does not resume until the Data Register is written with the next value to
send or until the stop or start bits are set, indicating that the current byte is the last one to
send.
The fourth interrupt source is the baud rate generator. If the I²C Controller is disabled
(IEN bit in the I2CCTL Register = 0) and the BIRQ bit in the I2CCTL Register = 1, an
interrupt is generated when the baud rate generator counts down to 1. This allows the I²C
baud rate generator to be used by software as a general purpose timer when IEN = 0.
Software Control of I²C Transactions
Software can control I²C transactions by using the I²C Controller interrupt, by polling the
I²C Status Register or by DMA. Note that not all products include a DMA Controller.
To use interrupts, the I²C interrupt must be enabled in the Interrupt Controller. The TXI bit
in the I²C Control Register must be set to enable transmit interrupts.
To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the I²C
Status Register should be polled. The TDRE bit asserts regardless of the state of the TXI
bit.
Either or both transmit and receive data movement can be controlled by the DMA Control-
ler. The DMA Controller channel(s) must be initialized to select the I²C transmit and
receive requests. Transmit DMA requests require that the TXI bit in the I²C Control Reg-
ister be set.
Caution: A transmit (write) DMA operation hangs if the slave responds with a Not Acknowledge
before the last byte has been sent. After receiving the Not Acknowledge, the I²C Control-
ler sets the NCKI bit in the Status Register and pauses until either the stop or start bits in
the Control Register are set. 

For a receive (read) DMA transaction to send a Not Acknowledge on the last byte, the
receive DMA must be set up to receive n-1 bytes, then software must set the NAK bit and
receive the last (nth) byte directly.
PS019924-0113
PRELIMINARY
Operation