Z8F4822AR020SG Datasheet, PDF (90/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
70
COMPARE Mode Time (s) = ^---C----o---m-----p---a--r--e----V-----a---l-u---e----–-----S---t--a---r--t---V----a---l-u---e----^---^-----P---r--e---s--c---a---l-e-
System Clock Frequency (Hz)
GATED Mode
In GATED Mode, the timer counts only when the timer input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control 1 Register. When the timer
input signal is asserted, counting begins. A timer interrupt is generated when the timer
input signal is deasserted or a timer reload occurs. To determine if a timer input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001H and counting resumes (assuming the timer input signal is still asserted).
Also, if the timer output alternate function is enabled, the timer output pin changes state
(from Low to High or from High to Low) at timer reset.
Observe the following procedure for configuring a timer for GATED Mode and initiating
the count:
1. Write to the Timer Control 1 Register to:
– Disable the timer
– Configure the timer for GATED Mode
– Set the prescale value
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in GATED Mode. After the first timer reset in GATED
Mode, counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the Timer Control 1 Register to enable the timer.
7. Assert the timer input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE Mode, the timer begins counting on the first external timer
input transition. The appropriate transition (rising edge or falling edge) is set by the TPOL
bit in the Timer Control 1 Register. The timer input is the system clock.
PS019924-0113
PRELIMINARY
Operation