Z8F4822AR020SG Datasheet, PDF (76/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
56
Bit
Field
RESET
R/W
Address
7
T2ENL
Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL)
6
T1ENL
5
T0ENL
4
3
U0RENL U0TENL
0
R/W
FC2H
2
I2CENL
1
0
SPIENL ADCENL
Bit
Description
[7]
Timer 2 Interrupt Request Enable Low Bit
T2ENL
[6]
Timer 1 Interrupt Request Enable Low Bit
T1ENL
[5]
Timer 0 Interrupt Request Enable Low Bit
T0ENL
[4]
UART 0 Receive Interrupt Request Enable Low Bit
U0RENL
[3]
U0TENL
[2]
I2CENL
UART 0 Transmit Interrupt Request Enable Low Bit
I²C Interrupt Request Enable Low Bit
[1]
SPI Interrupt Request Enable Low Bit
SPIENL
[0]
ADC Interrupt Request Enable Low Bit
ADCENL
IRQ1 Enable High and Low Bit Registers
Table 30 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters, shown in Tables 31 and 32, form a priority-encoded enabling for interrupts in the
Interrupt Request 1 Register. Priority is generated by setting bits in each register.
Table 30. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]
IRQ1ENL[x]
Priority
0
0
Disabled
0
1
Level 1
1
0
Level 2
1
1
Level 3
Note: x indicates register bits in the range [7:0].
Description
Disabled
Low
Nominal
High
PS019924-0113
PRELIMINARY
Interrupt Control Register Definitions