Z8F4822AR020SG Datasheet, PDF (70/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
50
• Writing a 1 to the IRQE bit in the Interrupt Control Register
Interrupts are globally disabled by any of the following operations:
• Execution of a Disable Interrupt (DI) instruction
• eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
• Writing a 0 to the IRQE bit in the Interrupt Control Register
• Reset
• Executing a trap instruction
• Illegal instruction trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of
the interrupts were enabled with identical interrupt priority (all as Level 2 interrupts, for
example), then the interrupt priority would be assigned from highest to lowest, as speci-
fied in Table 23. Level 3 interrupts always have higher priority than Level 2 interrupts
which, in turn, always have higher priority than Level 1 interrupts. Within each interrupt
priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 23.
Resets, Watchdog Timer interrupts (if enabled), and illegal instruction traps always have
highest priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the Interrupt Request Register is cleared until the next interrupt occurs. Writing a
0 to the corresponding bit in the Interrupt Request Register likewise clears the interrupt
request.
Caution: Zilog recommends not using a coding style that clears bits in the Interrupt Request reg-
isters. All incoming interrupts received between execution of the first LDX command
and the final LDX command are lost. See Example 1, which follows.
Example 1. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
PS019924-0113
PRELIMINARY
Operation