Z8F4822AR020SG Datasheet, PDF (254/323 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F64xx Series
Product Specification
234
Table 135. Rotate and Shift Instructions
Mnemonic
BSWAP
RL
RLC
RR
RRC
SRA
SRL
SWAP
Operands
dst
dst
dst
dst
dst
dst
dst
dst
Instruction
Bit Swap
Rotate Left
Rotate Left through Carry
Rotate Right
Rotate Right through Carry
Shift Right Arithmetic
Shift Right Logical
Swap Nibbles
eZ8 CPU Instruction Summary
Table 136 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags Register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
Table 136. eZ8 CPU Instruction Summary
Assembly
Mnemonic
ADC dst, src
Symbolic Operation
dst ← dst + src + C
Address
Mode
dst src
r
r
r Ir
RR
R IR
R IM
ADCX dst, src dst ← dst + src + C
IR IM
ER ER
ER IM
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
Opcode(s)
Flags
Fetch Instr.
(Hex) C Z S V D H Cycles Cycles
12
****0* 2
3
13
2
4
14
3
3
15
3
4
16
3
3
17
3
4
18
****0* 4
3
19
4
3
PS019924-0113
PRELIMINARY
eZ8 CPU Instruction Summary