MC9S12GRMV1 Datasheet, PDF (995/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

96 KByte Flash Module (S12FTMRG96K1V1)
Offset Module Base + 0x0005
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
0
0
0
DFDIE
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 28-10. Flash Error Configuration Register (FERCNFG)
0
SFDIE
0
All assigned bits in the FERCNFG register are readable and writable.
Table 28-14. FERCNFG Field Descriptions
Field
1
DFDIE
0
SFDIE
Description
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 28.3.2.8)
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see Section 28.3.2.8)
1 An interrupt will be requested whenever the SFDIF flag is set (see Section 28.3.2.8)
28.3.2.7 Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
Offset Module Base + 0x0006
R
W
Reset
7
CCIF
1
6
5
4
3
2
0
MGBUSY
RSVD
ACCERR
FPVIOL
0
0
0
0
0
1
0
MGSTAT[1:0]
0¹
0¹
= Unimplemented or Reserved
Figure 28-11. Flash Status Register (FSTAT)
1 _{Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see Section 28.6).}
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
997