MC9S12GRMV1 Datasheet, PDF (47/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Device Overview MC9S12G-Family
VDDR
VSS
BKGD
PE0
PE1
RESET
TEST
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
16K … 240K bytes Flash with ECC
1K … 11K bytes RAM
0.5K … 4K bytes EEPROM with ECC
Voltage Regulator
Input: 3.13V – 5.5V
CPU12-V1
Single-wire Background
Debug Module
Debug Module
3 comparators
64 Byte Trace Buffer
EXTAL
Low Power Pierce
XTAL ^Oscillator
PLL with Frequency
Modulation option
Reset Generation
and Test Entry
Clock Monitor
COP Watchdog
Real Time Interrupt
Auton. Periodic Int.
Internal RC Oscillator
Interrupt Module
3-5V IO Supply
VDDX1/VSSX1
VDDX2/VSSX2
VDDX3/VSSX3
DACU
DAC1
AMPM _{Digital-Analog}
AMP
Converter
AMPP
ACMP
Analog
Comparator
DAC0
Digital-Analog
Converter
ADC
12-bit or 10-bit
8...16 ch.
Analog-Digital
Converter
AN[15:0]
TIM
16-bit 6 … 8 channel
Timer
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PWM
8-bit 6 … 8 channel
Pulse Width Modulator
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
CAN
RXCAN
msCAN 2.0B
TXCAN
SCI2
RXD
Asynchronous Serial IF TXD
SCI0
Asynchronous Serial IF
SCI1
Asynchronous Serial IF
SPI0
Synchronous Serial IF
RXD
TXD
RXD
TXD
MISO
MOSI
SCK
SS
SPI1
Synchronous Serial IF
SPI2
Synchronous Serial IF
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
VDDA
VSSA
VRH
PAD[15:0]
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PM0
PM1
PM2
PM3
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
Block Diagram shows the maximum configuration!
Not all pins or all peripherals are available on all devices and packages.
Rerouting options are not shown.
Figure 1-1. MC9S12G-Family Block Diagram
1.6 Family Memory Map
Table 1-3 shows the MC9S12G-Family register memory map.
Table 1-3. Device Register Memory Map
Address
Module
0x0000–0x0009 PIM (Port Integration Module)
Size
(Bytes)
10
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
49