MC9S12GRMV1 Datasheet, PDF (592/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 18-4. CANCTL1 Register Field Descriptions (continued)
Field
1
SLPAK
0
INITAK
Description
Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see
Section 18.4.5.5, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request.
Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will
clear the flag if it detects activity on the CAN bus while in sleep mode.
0 Running — The MSCAN operates normally
1 Sleep mode active — The MSCAN has entered sleep mode
Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode
(see Section 18.4.4.5, “MSCAN Initialization Mode”). It is used as a handshake flag for the INITRQ initialization
mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,
CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by
the CPU when the MSCAN is in initialization mode.
0 Running — The MSCAN operates normally
1 Initialization mode active — The MSCAN has entered initialization mode
18.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
Module Base + 0x0002
Access: User read/write¹
7
R
SJW1
W
6
SJW0
5
BRP5
4
BRP4
3
BRP3
2
BRP2
Reset:
0
0
0
0
0
0
Figure 18-6. MSCAN Bus Timing Register 0 (CANBTR0)
1 _{Read: Anytime}
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
1
BRP1
0
0
BRP0
0
Table 18-5. CANBTR0 Register Field Descriptions
Field
Description
7-6
SJW[1:0]
5-0
BRP[5:0]
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see Table 18-6).
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see Table 18-7).
Table 18-6. Synchronization Jump Width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization Jump Width
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
MC9S12G Family Reference Manual, Rev.1.23
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Freescale Semiconductor