MC9S12GRMV1 Datasheet, PDF (757/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Timer Module (TIM16B8CV3)
Table 23-4. OC7M Field Descriptions
Field
Description
7:0
OC7M[7:0]
Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,
the output compare action reflects the corresponding OC7D bit.
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
a channel 7 event, even if the corresponding pin is setup for output compare.
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
channel 7 event.
Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to
be transferred from the output compare 7 data register to the timer port.
23.3.2.4 Output Compare 7 Data Register (OC7D)
1_.
Module Base + 0x0003
R
W
Reset
7
OC7D7
0
6
OC7D6
5
OC7D5
4
OC7D4
3
OC7D3
2
OC7D2
0
0
0
0
0
Figure 23-9. Output Compare 7 Data Register (OC7D)
1
OC7D1
0
0
OC7D0
0
Read: Anytime
Write: Anytime
Table 23-5. OC7D Field Descriptions
Field
Description
7:0
Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
OC7D[7:0] successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.
23.3.2.5 Timer Count Register (TCNT)
Module Base + 0x0004
R
W
Reset
15
TCNT15
0
14
TCNT14
13
TCNT13
12
TCNT12
11
TCNT11
10
TCNT10
0
0
0
0
0
Figure 23-10. Timer Count Register High (TCNTH)
9
TCNT9
0
9
TCNT8
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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