MC9S12GRMV1 Datasheet, PDF (321/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

S12S Debug Module (S12SDBGV2)
Table 8-14. State Control Register Access Encoding
COMRV
01
10
11
Visible State Control Register
DBGSCR2
DBGSCR3
DBGMFR
8.3.2.7.1 Debug State Control Register 1 (DBGSCR1)
Address: 0x0027
7
R
0
W
Reset
0
6
5
4
3
2
1
0
0
0
0
SC3
SC2
SC1
SC0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-9. Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1, “Debug Comparator Control
Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated
DBGXCTL control register.
Table 8-15. DBGSCR1 Field Descriptions
Field
3–0
SC[3:0]
Description
These bits select the targeted next state whilst in State1, based upon the match event.
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Table 8-16. State1 Sequencer Next State Selection
Description (Unspecified matches have no effect)
Any match to Final State
Match1 to State3
Match2 to State2
Match1 to State2
Match0 to State2....... Match1 to State3
Match1 to State3.........Match0 to Final State
Match0 to State2....... Match2 to State3
Either Match0 or Match1 to State2
Reserved
Match0 to State3
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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