MC9S12GRMV1 Datasheet, PDF (252/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
2.6 Initialization/Application Information
2.6.1 Initialization
After a system reset, software should:
1. Read the PKGCR and write to it with its preset content to engage the write lock on
PKGCR[PKGCR2:PKGCR0] bits protecting the device from inadvertent changes to the pin layout
in normal applications.
2. Write to PRR0 in 20 TSSOP to define the module routing and to PKGCR[APICLKS7] bit in any
package for API_EXTCLK.
GA240 / GA192 devices only:
3. In applications using the analog functions on port C pins shared with AMPM1, AMPP1 or DACU1
the input buffers should be disabled early after reset by enabling the related mode of the DAC1
module. This shortens the time of potentially increased power consumption caused by the digital
input buffers operating in the linear region.
2.6.2 Port Data and Data Direction Register writes
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins
from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data
register before enabling the outputs.
2.6.3 Enabling IRQ edge-sensitive mode
To avoid unintended IRQ interrupts resulting from writing to IRQCR while the IRQ pin is driven to active
level (IRQ=0) the following initialization sequence is recommended:
1. Mask I-bit
2. Set IRQCR[IRQEN]
3. Set IRQCR[IRQE]
4. Clear I-bit
2.6.4 ADC External Triggers ETRIG3-0
The ADC external trigger inputs ETRIG3-0 allow the synchronization of conversions to external trigger
events if selected as trigger source (for details refer to ATDCTL1[ETRIGSEL] and ATDCTL1[ETRIGCH]
configuration bits in ADC section). These signals are related to PWM channels 3-0 to support periodic
trigger applications with the ADC. Other pin functions can also be used as triggers.
If a PWM channel is routed to an alternative pin, the ETRIG input function will follow the relocation
accordingly.
If the related PWM channel is enabled, the PWM signal as seen on the pin will drive the ETRIG input. If
another signal of higher priority takes control of the pin or if on a port AD pin the input buffer is disabled,
MC9S12G Family Reference Manual, Rev.1.23
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Freescale Semiconductor