MC9S12GRMV1 Datasheet, PDF (713/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Serial Peripheral Interface (S12SPIV5)
Table 21-7. SPISR Field Descriptions
Field
5
SPTEF
4
MODF
Description
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to Table 21-9.
0 SPI data register not empty.
1 SPI data register empty.
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
Section 21.3.2.2, “SPI Control Register 2 (SPICR2)”. The flag is cleared automatically by a read of the SPI status
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
Table 21-8. SPIF Interrupt Flag Clearing Sequence
XFRW Bit
SPIF Interrupt Flag Clearing Sequence
0
Read SPISR with SPIF == 1 _then
Read SPIDRL
1
Read SPISR with SPIF == 1
Byte Read SPIDRL ¹
or
then Byte Read SPIDRH ² Byte Read SPIDRL
or
Word Read (SPIDRH:SPIDRL)
1 _{Data in SPIDRH is lost in this case.}
2 _{SPIDRH can be read repeatedly without any effect on SPIF. SPIF Flag is cleared only by the read}
of SPIDRL after reading SPISR with SPIF == 1.
Table 21-9. SPTEF Interrupt Flag Clearing Sequence
XFRW Bit
SPTEF Interrupt Flag Clearing Sequence
0
Read SPISR with SPTEF == 1 _then
Write to SPIDRL ¹
1 Read SPISR with SPTEF == 1
Byte Write to SPIDRL ¹²
or
then Byte Write to SPIDRH ¹³ Byte Write to SPIDRL ¹
or
Word Write to (SPIDRH:SPIDRL) ¹
1 _{Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.}
2 _{Data in SPIDRH is undefined in this case.}
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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