MC9S12GRMV1 Datasheet, PDF (760/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Timer Module (TIM16B8CV3)
23.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
Module Base + 0x0008
7
R
OM7
W
6
OL7
5
OM6
4
OL6
3
OM5
2
OL5
1
OM4
0
OL4
Reset
0
0
0
0
0
0
0
0
Figure 23-14. Timer Control Register 1 (TCTL1)
Module Base + 0x0009
7
R
OM3
W
6
OL3
5
OM2
4
OL2
3
OM1
2
OL1
1
OM0
0
OL0
Reset
0
0
0
0
0
0
0
0
Figure 23-15. Timer Control Register 2 (TCTL2)
Read: Anytime
Write: Anytime
Table 23-8. TCTL1/TCTL2 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
Field
7:0
OMx
7:0
OLx
Description
Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For
an output line to be driven by an OCx the OCPDx must be cleared.
Output Level — These eightpairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For
an output line to be driven by an OCx the OCPDx must be cleared.
Table 23-9. Compare Result Output Action
OMx
OLx
0
0
0
1
1
0
1
1
Action
No output compare
action on the timer output signal
Toggle OCx output line
Clear OCx output line to zero
Set OCx output line to one
MC9S12G Family Reference Manual, Rev.1.23
762
Freescale Semiconductor