MC9S12GRMV1 Datasheet, PDF (706/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Serial Peripheral Interface (S12SPIV5)
21.2.2 MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
21.2.3 SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
21.2.4 SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
21.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
21.3.1 Module Memory Map
The memory map for the SPI is given in Figure 21-2. The address listed for each register is the sum of a
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 7
0x0000
R
SPICR1 _W ^SPIE
0x0001
R
0
SPICR2 _W
0x0002
R
0
SPIBR
W
0x0003
SPISR
R SPIF
W
0x0004
R R15
SPIDRH _{W T15}
6
SPE
XFRW
SPPR2
0
5
4
3
SPTIE
MSTR
CPOL
0
MODFEN BIDIROE
0
SPPR1
SPPR0
SPTEF
MODF
0
R14
R13
R12
R11
T14
T13
T12
T11
= Unimplemented or Reserved
Figure 21-2. SPI Register Summary
2
CPHA
0
SPR2
0
R10
T10
1
SSOE
SPISWAI
SPR1
0
R9
T9
Bit 0
LSBFE
SPC0
SPR0
0
R8
T8
MC9S12G Family Reference Manual, Rev.1.23
708
Freescale Semiconductor