MC9S12GRMV1 Datasheet, PDF (178/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Port Integration Module (S12GPIMV1)
Table 2-15. Port J Pins PJ7-0 (continued)
PJ1
• Except 20 TSSOP and 32 LQFP: The SPI1 MOSI signal is mapped to this pin when used with the SPI
function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or
output.
• 48 LQFP: The TIM channel 6 signal is mapped to this pin when used with the timer function. The TIM
forces the I/O state to be an output for a timer port associated with an enabled output.
• Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
48 LQFP: MOSI1 > IOC6 > GPO
64/100 LQFP: MOSI1 > GPO
PJ0
• Except 20 TSSOP and 32 LQFP: The SPI1 MISO signal is mapped to this pin when used with the SPI
function. Depending on the configuration of the enabled SPI1 the I/O state is forced to be input or
output.
• 48 LQFP: The PWM channel 6 signal is mapped to this pin when used with the PWM function. The
enabled PWM channel forces the I/O state to be an output.
• Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
48 LQFP: MISO1 > PWM6 > GPO
64/100 LQFP: MISO1 > GPO
2.3.12
Pins AD15-0
NOTE
The following sources contribute to enable the input buffers on port AD:
• Digital input enable register bits set for each individual pin in ADC
• External trigger function of ADC enabled on ADC channel
• ADC channels routed to port C freeing up pins
• Digital input enable register set bit in and ACMP
Taking the availability of the different sources on each pin into account the
following logic equation must be true to activate the digital input buffer for
general-purpose input use:
IBEx = ( (ATDDIENH/L[IENx]=1) OR (ATDCTL1[ETRIGSEL]=0 AND ATDCTL2[ETRIGE]=1) OR
(PRR1[PRR1AN]=1) ) AND (ACDIEN=1)
Eqn. 2-1
MC9S12G Family Reference Manual, Rev.1.23
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