MC9S12GRMV1 Datasheet, PDF (403/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

10.4 Functional Description
S12 Clock, Reset and Power Management Unit (S12CPMU)
10.4.1 Phase Locked Loop with Internal Filter (PLL)
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK.
The REFCLK is by default the IRCCLK which is trimmed to f_{IRC1M_TRIM}=1MHz.
If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK
can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0]
bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock
by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,
3, 4, 5, 6,... to 32 to generate the PLLCLK.
If oscillator is enabled (OSCE=1)
If oscillator is disabled (OSCE=0)
f _REF = ₍---_R----_E----_F-^f--^OD-----^SI--_V-^C-----₊-----₁---₎-
fREF = fIRC1M
fVCO = 2 × fREF × (SYNDIV + 1)
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
f _PLL = ₍---_P----_O-----_S-^f--_T-^V---_D-^C----_I-^O-_V------₊-----₁---₎
f _PLL = ^f---^V----₄-^C----^O---
If PLL is selected (PLLSEL=1) f _bus = -^f--^P---₂-^L---^L--
.
NOTE
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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