MC9S12GRMV1 Datasheet, PDF (359/1292 Pages) Freescale Semiconductor, Inc – MC9S12G Family Reference Manual and Data Sheet

Chapter 10
S12 Clock, Reset and Power Management Unit (S12CPMU)
Revision History
Version Revision Effective
Number Date
Date
V04.10 01 Jul 10 01 Jul 10
V04.11 23 Aug 10 23 Aug 10
V04.12 27 April 12 27 April 12
Author
Description of Changes
Added TC trimming to feature list
Removed feature of adaptive oscillator filter. Register bits 6 and 4to
0in the CPMUOSC register are marked reserved and do not alter.
Corrected wording for API interrupt flag
Changed notation of IRC trim values for 0x00000 to 0b00000
10.1 Introduction
This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU).
• The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock
source. It is designed for optimal start-up margin with typical quartz crystals and ceramic
resonators.
• The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required
chip internal voltages and voltage monitors.
• The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
• The Internal Reference Clock (IRC1M) provides a1MHz clock.
10.1.1 Features
The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
• Supports quartz crystals or ceramic resonators from 4MHz to 16MHz.
• High noise immunity due to input hysteresis and spike filtering.
• Low RF emissions with peak-to-peak swing limited dynamically
• Transconductance (gm) sized for optimum start-up margin for typical crystals
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
361